The electrical interconnections between electronic devices are an important part of any functioning circuit. Improper interconnections can reduce the performance of a circuit or prevent the circuit from operating entirely. Traditionally, these interconnections have been made with various conductors including the metals copper and aluminum. In no area are good reliable interconnections more important than in integrated circuits.
The prior art process for interconnecting with a conductor the electronic devices on a silicon wafer is described as follows. Connecting these electronic devices is typically the final step in the construction of the integrated circuit and is also referred to as the metalization process. The process begins with the wafer containing completed electronic devices built into and onto the wafer. These electronic devices including bipolar and field effect transistors are not connected. The surface of the wafer appears smooth, but on the device scale the surface is uneven and contains sharp discontinuities generated as the electronic devices were constructed.
The first step of the prior art process for interconnecting the electronic devices is depositing a dielectric material on the uneven surface of the silicon wafer. Traditionally, the dielectric has been silicon dioxide. The silicon dioxide forms a thin layer on the surface of the wafer. This dielectric layer preserves and can accentuate the discontinuities on the surface of the wafer.
The second step is selectively removing the dielectric material to create holes which expose the contacts of the electronic devices. These holes are formed by selectively etching through the dielectric layer at specific locations. There are several well understood prior art methods for etching through the dielectric layer. These methods typically involve placing a photoresist on the surface of the device, exposing the photoresist to a particular wavelength of light, developing the photoresist to form a mask which exposes the dielectric material where it is to be removed, and removing the exposed dielectric material with either a wet or a dry etchant. Finally, the photoresist mask is removed exposing the dielectric layer.
The third step is depositing a conductor on the surface of the wafer. This conductor is typically aluminum, although other conductors may be used. Two different prior art method may be used to deposit the conductor. The methods are sputtering, where atoms of the conductor are knocked from a target made of the conductor and splattered onto the surface of the wafer, and evaporation, where the conductor is carried to the wafer in a vapor state and condenses on the surface of the wafer. In addition to providing a uniform layer of conductor on the wafer, this method must also fill the holes created in the previous step. These conductor filled holes are known as vias and serve as contacts to the electronic devices located below the dielectric layer.
The fourth and final step is removing selectively the conductor where it is not needed to form lines. The lines connect the electronic devices to form the desired circuit. This step is performed using a method which is very similar to the selective removal of dielectric and typically involves forming a photoresist mask and removing the conductor with an etchant.
This prior art process of interconnecting the electronic devices is referred to as a "subtractive" process since to form the lines which interconnect the electronic devices, the conductor is first deposited everywhere, then selectively removed. This process may be repeated as necessary to generate additional interconnection layers, although more than two interconnection layers are rare because of the problems described below.
The prior art process has several problems. The first and most severe problem is shorted and open lines.
Open lines occur in the prior art process when the conductor does not cover the sharp discontinuities on the surface of the wafer leaving gaps or opens in the lines. The source of these discontinuities is primarily the basic electronic devices which are built into and onto the wafer and the vias formed in previous process steps. When more than one interconnection layer is used, the problem is further aggravated by the lines in lower levels which themselves create discontinuities in higher layers. The problem is compounded when these discontinuities are accentuated by the typical method used to deposit the dielectric layer on the surface of the wafer. A discontinuity can be modeled by a higher horizontal surface, a first corner, a vertical surface, a second corner, and a lower horizontal surface. The first corner is exposed from the top and side. If this corner is 90 degrees, it has an angle of exposure of 270 degrees. However, the lower corner, if it is 90 degrees, has an angle of exposure of only 90 degrees. A flat surface, for example the higher and lower horizontal and vertical surfaces, are exposed from 180 degrees. Since the typical method of depositing the dielectric has a constant arrival rate, the rate of growth is dependent on the angle of exposure of the surface or corner. Therefore, the first corner, which is exposed more than any other surface, grows the fastest. In fact the first corner grows so fast, faster than the higher horizontal surface, that it begins to rise up above that surface accentuating the discontinuity represented by the original corner.
When the conductor is deposited on the dielectric covered discontinuities, the first corner growth will shadow or mask the vertical surface and the second corner by reducing the angle of exposure. The reduced angle of exposure of the vertical surface and the second corner, reduces the growth rate on those surfaces causing a very thin layer of conductor to be applied or even possibly leaving an open in the conductor. Even assuming that the vertical wall has no opens after the conductor has been deposited as described above, opens may still develop in the thinly coated walls of the via or in any other thinly coated location. Although the thin spot may test as a complete circuit immediately after construction, the conductor may eventually open due to electromigration. The thinner the conductor is, the higher the flux density for a given current will be through the conductor. The increased flux density in the narrow region may cause electromigration of the conductor atoms resulting in the atoms at the thin spot moving to a thicker spot. This causes the thin spot to become even thinner, eventually resulting in an open. Electromigration is particularly a problem when aluminum is the conductor.
Open and shorted lines also occur in the prior art process when the layer of the conductor is improperly etched. Shorts may be caused by underetching. Underetching occurs when all of the conductor is not removed by the etchant leaving the conductor, for example, between two lines forming a short. Opens and thin spots may be created by overetching, removing too much conductor, or undercutting. Etching occurs where the conductor is exposed through a mask to the etchant, however, what is etched depends on whether the etchant is isotropic or anisotropic. An isotropic etchant etches the conductor at a constant rate in all directions. An anisotropic etchant etches in one direction more rapidly than any other. If the etchant is isotropic in nature, the etchant will begin to dissolve the exposed material, but in all directions. This causes the removal of the conductor directly under the mask and is referred to as undercutting. A certain amount of undercutting is normal. When the conductor is deposited on the surface of the wafer, the conductor will form large overhangs at discontinuities on the wafer for reasons similar to that for the dielectric. When large overhangs are present on the wafer, the conductor must be exposed to the etchant for a longer period of time to prevent shorts. This leads to excessive undercutting which may cause open lines, or thin spots.
If an anisotropic etchant is used, the etchant will begin to dissolve the exposed material but primarily in one direction toward the wafer. Therefore, undercutting is considerably reduced when an anisotropic etchant is used. However, the etchant may leave conductor in the bottom of a discontinuity, thereby causing shorts. This may be understood by referring to the model of a discontinuity above. The etchant must first remove the large overhang of conductor on the first corner and the vertical wall before removing the conductor in the second corner. Because the quantity of conductor which must be removed is considerably more than in any other place on the wafer the etching process may be stopped before the etchant has removed the conductor in the second corner. The conductor remaining in the second corner causes a short between two lines. As geometries approach the one micron level shorts and opens caused by the etching process become an increasing problem.
The second problem with the prior art process is electrically open vias. The vias begin as holes in the dielectric etched in the second step of the prior art process. When the conductor is deposited in the third step, it first covers the top of the dielectric layer and the bottom of the hole. Because the top of the hole has a higher angle of exposure, it begins to build more rapidly, as occurred above with the dielectric at a discontinuity. The excess material at the top of the hole will tend to shadow or mask the vertical walls of the hole, thereby causing the vertical surfaces of the hole to remain uncovered. Absence of the conductor on the side of the via leaves the top and the bottom of the via unconnected causing an open circuit. This problem also becomes more serious as integrated circuit geometries are reduced. One method of depositing the conductor tungsten called chemical vapor deposition has been used to reduce the problem. However, even when the surface surrounding the top and the bottom of the via are properly connected, a dimple is formed at the top of the via. This dimple causes further discontinuities for later interconnect layers.
Finally, a third problem occurs as geometries of the lines are reduced as required for VLSI integrated circuits. The ratio between the height of the line and the width of the line is referred to as the aspect ratio. When the geometries of the lines and vias are reduced, the aspect ratio increases because the lines of the conductor which form the interconnections between the electronic devices are reduced in width, but not in height. As the width of the line becomes narrower, there is less area between the line and the dielectric layer. Therefore there is less area to adhere to the dielectric. The height of the conductor line however is not reduced so the internal forces remain as strong as before. When the internal forces exceed the adhesion force, which occurs more frequently with a high aspect ratio, the line lifts off of the dielectric layer and ruins the integrated circuit.
The prior art means to reducing the problem is to reduce the height of the line. Reducing the height of the line reduces the cross sectional area of the line which increases the resistance of the line. In VLSI circuits where the lines are at the one micron and submicron levels, the line may actually require a very large electronic device to drive the line at a high speed. Since such large devices would operate too slowly, a smaller device and shorter line must be used. This condition is referred to as "wire limited" circuitry and severely restricts circuit design and organization and is therefore undesirable. Also since the prior art process is basically a subtractive process, any overetching during the fourth step of the metalization process will also reduce the width of the lines and cause the same problems with adhesion and "wire limiting" as caused by a reduction in the geometries.